Conquering noise in deep-submicron digital ICs

Conquering Noise in Deep-Submicron Digital ICs

Identifying defects in deep-submicron CMOS ICs

Given the oft-cited difficulty of testing modern integrated circuits, the fact that CMOS ICs lend themselves to IDDQ testing is a piece of good fortune. But that valuable advantage is threatened by the rush of semiconductor technology to smaller feature sizes and faster, denser circuits, in line with the Semiconductor Industry Association's (SIA) Roadmap--its forecast for the CMOS IC industry. ...

Harmony: static noise analysis of deep submicron digital integrated circuits

As technology scales into the deep submicron regime, noise immunity is becoming a metric of comparable importance to area, timing, and power for the analysis and design of very large scale integrated (VLSI) systems. A metric for noise immunity is defined, and a static noise analysis methodology based on this noise-stability metric is introduced to demonstrate how noise can be analyzed systemati...

Crosstalk effects in mixed-signal ICs in deep submicron digital CMOS technology

This paper illustrates the crosstalk phenomenon and its impact on the design of mixed analog/digital circuits with high accuracy specifications. Generation of digital disturbs, propagation through the substrate, and effects on analog devices are considered, with particular emphasis on integrated circuits realized on heavily doped substrate, where traditional shielding is less effective. Techniq...

Feasibility of IDDQ Tests for Shorts in Deep Submicron ICs

Quiescent supply current(IDDQ) in deep submicron ICs is derived by circuit simulation and feasibility of IDDQ tests is examined for short defects in ICs fabricated with 0.18μm CMOS process. The results show that IDDQ of each gate depends on input logic values and that shorts can be detected by IDDQ testing if some process variations are small.